The embodiments disclosed herein relate to characterizing parasitic resistances in integrated circuits and, more particularly, to embodiments of a test structure as well as a system, a method and a computer program product for characterizing interface resistance in a multi-layer conductive structure, such as a multi-layer ohmic contact.
Parasitic contact resistance is one of the larger parasitic resistances that will impact the performance of very large scale integration (VLSI) circuits, such as ring oscillators, logic gates (e.g., NAND gates, NOR gates, etc.), etc. Thus, accurate characterization of parasitic contact resistance is very important in integrated circuit design. Traditionally, contact resistance is characterized based on current-voltage measurements acquired from a test structure comprising a transmission line model (TLM) structure formed on a semiconductor substrate. However, this characterization does not uniquely characterize the resistance of individual layers within a multi-layer contact, nor does it characterize the interface resistance between such layers.